Field of the Invention
The present invention relates to a solid-state imaging device for use in a digital camera, a digital video camera, an endoscope, and the like.
Description of the Related Art
A column analog-to-digital (A/D) type solid-state imaging device is known as a means for performing A/D conversion on a pixel signal read from a pixel and implementing high-speed reading of a pixel signal (for example, see Japanese Unexamined Patent Application, First Publication No. 2005-323331, hereinafter referred to as Patent Literature 1). FIG. 8 illustrates a configuration equivalent to a solid-state imaging device disclosed in Patent Literature 1.
The solid-state imaging device illustrated in FIG. 8 includes a pixel unit 1000, an A/D conversion circuit 1001, a vertical scanning circuit 1002, a horizontal scanning circuit 1003, a sense amplifier 1004, and a control circuit 1005. The pixel unit 1000 has a plurality of pixels 1006 disposed in a matrix and generates a pixel signal. The pixel 1006 has a photoelectric conversion element for converting incident light into an electric signal and generates a pixel signal. The A/D conversion circuit 1001 constitutes a so-called single-sloped A/D conversion circuit (SSADC), and includes a digital-to-analog converter (DAC) 1007, a comparator 1008, and a counter memory 1009. The comparator 1008 and the counter memory 1009 are arranged for every pixel column.
The DAC 1007 generates a ramp signal RAMP that varies stepwise. The comparator 1008 generates a pulse signal having a pulse width corresponding to a magnitude of the pixel signal based on the ramp signal RAMP generated by the DAC 1007 and the pixel signal read from the pixel 1006. The counter memory 1009 has a counter and a memory. The counter is constituted of a plurality of counter units (1-bit counters), and converts a pulse width of a pulse signal into a digital signal by (a count operation of) counting a count clock CNTCLK having a known frequency in a period according to the pulse signal generated by the comparator 1008. The memory is constituted of a plurality of memory units (1-bit memories), holds a signal based on a count value, and outputs the held signal to a horizontal signal transfer line HTL disposed in a horizontal direction according to horizontal transfer control signals H1 to H4 generated by the horizontal scanning circuit 1003 (horizontal transfer operation).
The vertical scanning circuit 1002 controls an operation of the pixel 1006. The horizontal scanning circuit 1003 generates the horizontal transfer control signals H1 to H4 for outputting the signal held by the memory of the counter memory 1009 to the horizontal signal transfer line HTL. The sense amplifier 1004 outputs the signal output to the horizontal signal transfer line HTL as an imaging signal. The control circuit 1005 generates a clock for controlling the DAC 1007, a count clock CNTCLK serving as a clock to be counted by the counter unit of the counter memory 1009, and a holding timing control signal LATCH for controlling an operation in which the memory unit of the counter memory 1009 holds a signal based on a count value. In addition, the control circuit 1005 generates a control signal for controlling the operations of the vertical scanning circuit 1002 and the horizontal scanning circuit 1003.
The solid-state imaging device illustrated in FIG. 8 implements high-speed signal reading by performing pipeline processing on a count operation and a horizontal transfer operation in an operation of reading the pixel signal. That is, the solid-state imaging device illustrated in FIG. 8 holds a signal based on counting at the time of first A/D conversion in the memory and performs second A/D conversion (a count operation) simultaneously when the signal is horizontally transferred.
There is a problem in that a layout region available in the A/D conversion circuit configured to perform A/D conversion for every pixel column is limited to a fine pixel width. Thus, the number of signal lines passing through a vertical direction is also limited by a layout limit.
FIG. 9 illustrates a layout example of the counter units and the memory units constituting the counter memory 1009 for one column. The counter units 1011 which are 1-bit counters are arranged in the vertical direction (column direction) and the memory units 1012 which are 1-bit memories are arranged between the counter units 1011. The memory units 1012 are connected to the horizontal signal transfer lines HTL1 to HTL3 via a switch 1013.
The counter unit 1011 performs a count operation at a rising or falling timing of an input clock and outputs a signal (clock) according to a state of a count value. The counter unit 1011 arranged on the uppermost side in FIG. 9 is a least significant bit (LSB) counter unit 1011 and the count clock CNTCLK is input thereto. The counter unit 1011 outputs a clock to the memory unit 1012 and the higher-bit counter unit 1011.
The memory unit 1012 holds an input signal (high or low state) based on a holding timing control signal LATCH. Each memory unit 1012 is connected to the switch 1013. The switch 1013 can be switched between ON and OFF. In the case of ON, a signal held in the memory unit 1012 is output to the horizontal signal transfer lines HTL1 to HTL3. The switching of ON and OFF of the switch 1013 is performed based on the horizontal transfer control signal Hn (n: column number; in FIG. 9, n is 1 to 4).
In first A/D conversion, each counter unit 1011 counts a count clock CNTCLK or a clock output from the lower-bit counter unit 1011. The comparator 1008 compares voltages of a ramp signal RAMP and a pixel signal and inverts an output when a magnitude relationship between the voltages of the ramp signal RAMP and the pixel signal is reversed. At a point in time at which a signal output from the comparator 1008 has been inverted, each counter unit 1011 stops a count operation. Thereby, a state of a signal output from each counter unit 1011 becomes regular. Subsequently, the memory units 1012 simultaneously hold signals output from the counter units 1011 based on the holding timing control signal LATCH.
Subsequently, a horizontal transfer of signals from the memory units 1012 to the horizontal signal transfer lines HTL1 to HTL3 and second A/D conversion are performed in parallel. In the second A/D conversion, each counter unit 1011 performs a count operation as in the first A/D conversion. While the counter unit 1011 performs the count operation, the memory units 1012 simultaneously output held signals to the horizontal signal transfer lines HTL1 to HTL3 based on the horizontal transfer control signal Hn. At a point in time at which a signal output from the comparator 1008 has been inverted, each counter unit 1011 stops a count operation. Subsequently, as described above, the signal holding and the horizontal transfer operation by the memory unit 1012 are performed.
As illustrated in FIG. 9, the counter unit 1011 and the memory unit 1012 corresponding to each bit are disposed in the vertical direction, so that it is possible to minimize the number of signal lines of the vertical direction and the layout is implemented within a limited width. However, this has the following disadvantages.
The horizontal signal transfer lines HTL1 to HTL3 intersect a signal line through which a clock output from the counter unit 1011 is transferred in all columns. Thus, one disadvantage is that a signal of a first A/D conversion result held in the memory unit 1012 is affected by noise due to driving of the counter unit 1011 of each column while the counter units 1011 of all the columns simultaneously perform count operations in the second A/D conversion. The noise due to the driving of the counter unit 1011 becomes a factor of an error of a signal transfer.
In order to solve the above-described problem, a layout method of dividing a counter group and a memory group is proposed (for example, see Patent Literature 2). FIG. 10 illustrates a layout example like the layout proposed in Japanese Unexamined Patent Application, First Publication No. 2009-89050, hereinafter referred to as Patent Literature 2. In FIG. 10, a counter group Gc and a memory group Gm are arranged. The counter group Gc includes three counter units 1011a, 1011b, and 1011c and three switches 1013a, 1013b, and 1013c. The counter group Gc includes three memory units 1012a, 1012b, and 1012c and three switches 1014a, 1014b, and 1014c. 
The counter units 1011a, 1011b, and 1011c are disposed in the vertical direction. The switch 1013a is connected to the counter unit 1011a and the vertical signal transfer line VTL1 disposed in the vertical direction. The switch 1013b is connected to the counter unit 1011b and the vertical signal transfer line VTL1. The switch 1013c is connected to the counter unit 1011c and the vertical signal transfer line VTL1. The switches 1013a, 1013b, and 1013c can be switched between ON and OFF, and output signals output from the counter units 1011a, 1011b, and 1011c to the vertical signal transfer line VTL1 in the case of ON. The switching between ON and OFF of the switches 1013a, 1013b, and 1013c is performed based on output timing control signals COUT1 to COUT3.
The memory units 1012a, 1012b, and 1012c are disposed in the vertical direction. The memory units 1012a, 1012b, and 1012c are connected to the vertical signal transfer line VTL1, and hold a signal output to the vertical signal transfer line VTL1 based on holding timing control signals LATCH1 to LATCH3. The switch 1014a is connected to the memory unit 1012a and the horizontal signal transfer line HTL1 disposed in the horizontal direction. The switch 1014b is connected to the memory unit 1012b and the horizontal signal transfer line HTL2 disposed in the horizontal direction. The switch 1014c is connected to the memory unit 1012c and the horizontal signal transfer line HTL3 disposed in the horizontal direction. The switches 1014a, 1014b, and 1014c can be switched between ON and OFF, and output signals output from the memory units 1012a, 1012b, and 1012c to the horizontal signal transfer lines HTL1 to HTL3 in the case of ON. The switching between ON and OFF of the switches 1014a, 1014b, and 1014c is performed based on horizontal transfer control signals Hn (n: column number; in FIG. 10, n is 1 to 4).
In the circuit illustrated in FIG. 10, a count operation and a horizontal transfer operation are performed in parallel as follows. In first A/D conversion, after the counter units 1011a, 1011b, and 1011c have stopped the count operations, the control signal is sequentially varied by a combination of the output timing control signal COUT1 and the holding timing control signal LATCH1, a combination of the output timing control signal COUT2 and the holding timing control signal LATCH2, a combination of the output timing control signal COUT3 and the holding timing control signal LATCH3, and signals are transferred from the counter units 1011a, 1011b, and 1011c to the memory units 1012a, 1012b, and 1012c. 
First, the switch 1013a is turned on based on the output timing control signal COUT1 and the holding timing control signal LATCH1, and the memory unit 1012a holds a signal output to the vertical signal transfer line VTL1. Subsequently, based on the output timing control signal COUT2 and the holding timing control signal LATCH2, the switch 1013b is turned on and the memory unit 1012b holds a signal output to the vertical signal transfer line VTL1. Subsequently, based on the output timing control signal COUT3 and the holding timing control signal LATCH3, the switch 1013c is turned on and the memory unit 1012c holds a signal output to the vertical signal transfer line VTL1. In this manner, signals based on count values of the counter units 1011a, 1011b, and 1011c are held in the memory units 1012a, 1012b, and 1012c in time division.
After signals are held in all the memory units 1012a, 1012b, and 1012c, the counter units 1011a, 1011b, and 1011c perform count operations in second A/D conversion. While the counter units 1011a, 1011b, and 1011c perform the count operations, the memory units 1012a, 1012b, and 1012c simultaneously output the held signals to the horizontal signal transfer lines HTL1 to HTL3 based on the horizontal transfer control signal Hn.
Because a counter group Gc and a memory group Gm are divided in the circuit illustrated in FIG. 10, noise due to driving of the counter units 1011a, 1011b, and 1011c is not superimposed on the horizontal signal transfer lines HTL1 to HTL3 even when count operations by the counter units 1011a, 1011b, and 1011c and horizontal transfer operations by the memory units 1012a, 1012b, and 1012c are simultaneously performed. Thus, it is possible to implement high-speed signal reading and implement a circuit robust to noise.